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static void dma0_ch0_isr(void *arg);
static void adc_init(void)
{
struct bflb_adc_channel_s chan[] = {
{ .pos_chan = ADC_CHANNEL_0,
.neg_chan = ADC_CHANNEL_GND },
{ .pos_chan = ADC_CHANNEL_3,
.neg_chan = ADC_CHANNEL_GND },
};
adc = bflb_device_get_by_name("adc");
/**
* adc clock = XCLK / 2 / 20 / 64(14B) = 15.625K
*/
struct bflb_adc_config_s cfg;
cfg.clk_div = ADC_CLK_DIV_20;
cfg.scan_conv_mode = true;
cfg.continuous_conv_mode = true;
cfg.differential_mode = false;
cfg.resolution = ADC_RESOLUTION_14B;
cfg.vref = ADC_VREF_2P0V;
bflb_adc_init(adc, &cfg);
bflb_adc_channel_config(adc, chan, sizeof(chan) / sizeof(chan[0]));
bflb_adc_link_rxdma(adc, true);
struct bflb_device_s *dma0_ch0;
dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
struct bflb_dma_channel_config_s config;
config.direction = DMA_PERIPH_TO_MEMORY;
config.src_req = DMA_REQUEST_ADC;
config.dst_req = DMA_REQUEST_NONE;
config.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.src_burst_count = DMA_BURST_INCR1;
config.dst_burst_count = DMA_BURST_INCR1;
config.src_width = DMA_DATA_WIDTH_32BIT;
config.dst_width = DMA_DATA_WIDTH_32BIT;
bflb_dma_channel_init(dma0_ch0, &config);
bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
static struct bflb_dma_channel_lli_pool_s lli[20]; /* max trasnfer size 4064 * 20 */
static struct bflb_dma_channel_lli_transfer_s transfers[2];
transfers[0].src_addr = (uint32_t)DMA_ADDR_ADC_RDR;
transfers[0].dst_addr = (uint32_t)adc_raw_data[0];
transfers[0].nbytes = sizeof(adc_raw_data[0]);
transfers[1].src_addr = (uint32_t)DMA_ADDR_ADC_RDR;
transfers[1].dst_addr = (uint32_t)adc_raw_data[1];
transfers[1].nbytes = sizeof(adc_raw_data[1]);
int used_count = bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 2);
bflb_dma_channel_lli_link_head(dma0_ch0, lli, used_count);
bflb_dma_channel_start(dma0_ch0);
// bflb_adc_start_conversion(adc);
bflb_adc_stop_conversion(adc);
}
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